TechiTips - Building Your First FPGA or CPLD Design

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A VERY SIMPLE LIST OF THINKS TO DO AND CHECK WHEN YOU BUILD YOUR FIRST DESIGN

We have started this page to ease your way into CPLD and FPGA design. It is based on the Xilinx ISE flow but generally applies to other vendor tools. We hope to expand this page with screenshots and other materials eventually. For the moment it is merely a check list of things to do and check.

(1) Prepare you design using schematics, VHDL or Verilog. Tools like ISE have editors to create and edit schematics, VHDL or Verilog sources.

(2) If you prepared your source outside of ISE you need to add it to the list of sources. ISE will usually sort out the heirarchy of files for you but do check. If a file is shown outside the heirarchy then it has not linked in correctly. One thing to check is the linkage e.g. in VHDL the "ENTITY" name should be the same as the component declaration in the file above or in the package file if one of those is being used.

(3) Run the synthesiser and clear all errors.

(4) Run the utility (PACE) to set pin numbers. Assign all pins to the locations you need. If you do not lock down pins the place and route tool will randomly place these pins.

(5) Set a basic timing constraints. Set a frequency/period for your clock as a minimum. Using constraints for clock to output - offset out and setup - offset in are also worth doing.

(6) Now run MAP and PLACE & ROUTE. Check that your timing has been achieved.

(7) Generate FPGA programming file - BIT file.

(8) Generate the file for your PROM if using one or more of these to load the FPGA.

(9) Load your PROM or FPGA. If using a PROM there is an option to load the FPGA after PROM load. Some systems may need a power cycle e.g. PCI based cards need reconfiguration of parameters by the system.

Common First Time Mistakes

(1) Asynchronous Inputs - Asynchronous inputs can cause unusual state machine or other logic operation if not properly designed for. Typically you may see a state machine jump states or even enter an illegal state. Ways to cope with this problem include (a) Synchronise inputs to clock with double or treble registers to minimise metastability. (2) Encode state machines with grey encode such that only a single flip-flop "looks" at the input.

(2) Pins not assigned - Input stimulus does not appear to work or outputs do not appear to work. Solution - lock down pins in UCF file either using graphical editor "PACE" or text editor.

(3) Tools complain of incompatible pins - Unlike early versions later versions of ISE usually need the I/O standard to be set for 3.3V pins. FPGAs are are typically arranged in banks and usually within a bank only certain combinations of I/O types can be used. Ensure that your mixture of I/O types is compatible. Usually pins operating at the same voltage are compatible but do check the datasheet of your device for other limitations.

(4) Many modern FPGAs are not 5V tolerant. If using 5V logic, e.g, 74HC family, ensure that you can meet external input voltage levels (5V CMOS VIH is 3.5v to 4.0V and can not be reached by a FPGA with a 3.3V drive) and that external driven signals routed to your FPGA do not exceed the input capablity of your FPGA. Special measures can be use to interface such multi-level systems. Some of our other TechiTips cover these topics.