------------------------------------------------------------------------------- -- (c) Enterpoint Ltd ------------------------------------------------------------------------------- -- -- Customer: -- Project: -- Filename: OPB_RAM3.VHD -- Version: 1.0 -- -- Author: John Adair -- Company: Enterpoint Ltd. -- Unit 4 -- Malvern Hills Science Park -- Geraldine Road -- Malvern -- United Kingdom -- WR14 3SZ -- -- Phone: 01684 585262 -- Email: pciopb@enterpoint.co.uk -- -- Change History: -- Date Version Comments -- 05/12/2005 1.0 Draft - needs checking -- -- -- -- Description: -- Demo of code -- -- -- -- ----------------------------------------------------------------- -- -- ----------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; --TRANSLATE OFF library unisim; use unisim.vcomponents.all; --TRANSLATE ON ENTITY OPB_RAM1 IS GENERIC( OPB_RAM1_DPM_BASEADDR : STD_LOGIC_VECTOR:= X"A0000000"; OPB_RAM1_DPM_HIGHADDR : STD_LOGIC_VECTOR:= X"A00001FF"); PORT( CLK : IN STD_LOGIC; RST : IN STD_LOGIC; PORT_ID : IN STD_LOGIC_VECTOR(7 DOWNTO 0); LE_DATAOUT : IN STD_LOGIC_VECTOR(7 DOWNTO 0); LE_WRITE_STROBE : IN STD_LOGIC; LE_READ_STROBE : IN STD_LOGIC; PASS_RAM_LE_DATAIN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); OPB_RAM1_INTERRUPT : OUT STD_LOGIC; OPB_ABUS : IN STD_LOGIC_VECTOR(0 TO 31); OPB_SELECT : IN STD_LOGIC; OPB_BE : IN STD_LOGIC_VECTOR(0 TO 3); OPB_RNW : IN STD_LOGIC; OPB_SEQADDR : IN STD_LOGIC; OPB_DBUS_IN : IN STD_LOGIC_VECTOR(0 TO 31); OPB_RAM1_OPB_DBUS_OUT : OUT STD_LOGIC_VECTOR(0 TO 31); OPB_RAM1_XFERACK : OUT STD_LOGIC; --ACK PCI AS SLAVE OPB_RAM1_RETRY : OUT STD_LOGIC; --RETRY OPB_RAM1_TOUTSUP : OUT STD_LOGIC; --TIMEOUT SUPPRESS OPB_RAM1_ERRACK : OUT STD_LOGIC); END OPB_RAM1; ARCHITECTURE A0 OF OPB_RAM1 IS --CONSTANT TO STABALISE SIM CONSTANT SIM_DELAY : TIME:= 1 nS; ----- Component RAMB16_S18_S36 ----- component RAMB16_S9_S36 -- generic ( WRITE_MODE_A : string := "WRITE_FIRST"; WRITE_MODE_B : string := "WRITE_FIRST"; INIT_A : bit_vector := b"000000000"; SRVAL_A : bit_vector := b"000000000"; INIT_B : bit_vector := X"000000000"; SRVAL_B : bit_vector := X"000000000"; INITP_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INITP_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_00 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_01 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_02 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"; INIT_03 : bit_vector := X"0000000000000000000000000000000000000000000000000000000000000000"); -- port (DIA : in STD_LOGIC_VECTOR (7 downto 0); DIB : in STD_LOGIC_VECTOR (31 downto 0); DIPA : in STD_LOGIC_VECTOR (0 downto 0); DIPB : in STD_LOGIC_VECTOR (3 downto 0); ENA : in STD_logic; ENB : in STD_logic; WEA : in STD_logic; WEB : in STD_logic; SSRA : in STD_logic; SSRB : in STD_logic; CLKA : in STD_logic; CLKB : in STD_logic; ADDRA : in STD_LOGIC_VECTOR (10 downto 0); ADDRB : in STD_LOGIC_VECTOR (8 downto 0); DOA : out STD_LOGIC_VECTOR (7 downto 0); DOB : out STD_LOGIC_VECTOR (31 downto 0); DOPA : out STD_LOGIC_VECTOR (0 downto 0); DOPB : out STD_LOGIC_VECTOR (3 downto 0)); end component; SIGNAL PULLUP_16 : STD_LOGIC_VECTOR(15 DOWNTO 0); SIGNAL PULLUP_4 : STD_LOGIC_VECTOR( 3 DOWNTO 0); SIGNAL PULLUP_2 : STD_LOGIC_VECTOR( 1 DOWNTO 0); SIGNAL PULLUP : STD_LOGIC_VECTOR( 0 DOWNTO 0); SIGNAL LITTLE_ENDIAN_OPB_DATA : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL ADDRB : STD_LOGIC_VECTOR(8 DOWNTO 0); SIGNAL PULLDOWN : STD_LOGIC; SIGNAL CLK_INVERTED : STD_LOGIC; SIGNAL WEB : STD_LOGIC; SIGNAL OPB_RAM1_DATAOUT : STD_LOGIC_VECTOR(31 DOWNTO 0); SIGNAL PORTB_EN : STD_LOGIC; SIGNAL PORTA_EN : STD_LOGIC; SIGNAL INT_OPB_RAM1_XFERACK : STD_LOGIC; SIGNAL ADDRESS : STD_LOGIC_VECTOR(10 DOWNTO 0); SIGNAL INT_OPB_RAM1_INTERRUPT : STD_LOGIC; SIGNAL PORTB_EN_DEL1 : STD_LOGIC; SIGNAL LOWADDR : STD_LOGIC_VECTOR(0 TO 31); SIGNAL HIGHADDR : STD_LOGIC_VECTOR(0 TO 31); BEGIN LOWADDR <= OPB_RAM1_DPM_BASEADDR; HIGHADDR <= OPB_RAM1_DPM_HIGHADDR; OPB_RAM1_XFERACK <= INT_OPB_RAM1_XFERACK; OPB_RAM1_INTERRUPT <= INT_OPB_RAM1_INTERRUPT; --AIM TO PULL IN TO MACRO INVERTERS CLK_INVERTED <= NOT CLK; PULLUP_16 <= (OTHERS => '1'); PULLUP_2 <= (OTHERS => '1'); PULLUP_4 <= (OTHERS => '1'); PULLUP <= (OTHERS => '1'); PULLDOWN <= '0'; -- DATAINREG : PROCESS(CLK) -- BEGIN -- IF (CLK'event AND CLK='1') THEN --ENDIAN SWITCHES LITTLE_ENDIAN_OPB_DATA(31) <= OPB_DBUS_IN(0) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(30) <= OPB_DBUS_IN(1) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(29) <= OPB_DBUS_IN(2) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(28) <= OPB_DBUS_IN(3) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(27) <= OPB_DBUS_IN(4) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(26) <= OPB_DBUS_IN(5) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(25) <= OPB_DBUS_IN(6) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(24) <= OPB_DBUS_IN(7) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(23) <= OPB_DBUS_IN(8) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(22) <= OPB_DBUS_IN(9) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(21) <= OPB_DBUS_IN(10) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(20) <= OPB_DBUS_IN(11) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(19) <= OPB_DBUS_IN(12) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(18) <= OPB_DBUS_IN(13) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(17) <= OPB_DBUS_IN(14) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(16) <= OPB_DBUS_IN(15) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(15) <= OPB_DBUS_IN(16) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(14) <= OPB_DBUS_IN(17) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(13) <= OPB_DBUS_IN(18) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(12) <= OPB_DBUS_IN(19) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(11) <= OPB_DBUS_IN(20) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(10) <= OPB_DBUS_IN(21) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(9) <= OPB_DBUS_IN(22) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(8) <= OPB_DBUS_IN(23) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(7) <= OPB_DBUS_IN(24) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(6) <= OPB_DBUS_IN(25) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(5) <= OPB_DBUS_IN(26) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(4) <= OPB_DBUS_IN(27) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(3) <= OPB_DBUS_IN(28) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(2) <= OPB_DBUS_IN(29) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(1) <= OPB_DBUS_IN(30) AFTER SIM_DELAY; LITTLE_ENDIAN_OPB_DATA(0) <= OPB_DBUS_IN(31) AFTER SIM_DELAY; -- END IF; -- END PROCESS DATAINREG; ADDRESS <= "000" & PORT_ID AFTER SIM_DELAY; --USE FALLING EDGE TO REDUCE LATENCY ACK : PROCESS(RST,CLK) BEGIN IF (RST = '1') THEN INT_OPB_RAM1_XFERACK <= '0'; OPB_RAM1_ERRACK <= '0' AFTER SIM_DELAY; OPB_RAM1_RETRY <= '0' AFTER SIM_DELAY; OPB_RAM1_TOUTSUP <= '0' AFTER SIM_DELAY; ELSIF (CLK'event AND CLK='0') THEN IF (OPB_RNW = '0') THEN INT_OPB_RAM1_XFERACK <= PORTB_EN AFTER SIM_DELAY; ELSE INT_OPB_RAM1_XFERACK <= (PORTB_EN AND PORTB_EN_DEL1) AFTER SIM_DELAY; END IF; OPB_RAM1_ERRACK <= '0' AFTER SIM_DELAY; OPB_RAM1_RETRY <= '0' AFTER SIM_DELAY; OPB_RAM1_TOUTSUP <= '0' AFTER SIM_DELAY; END IF; END PROCESS ACK; en : PROCESS(OPB_SELECT, OPB_ABUS) BEGIN IF ((OPB_SELECT = '1') AND (OPB_ABUS >= OPB_RAM1_DPM_BASEADDR) AND (OPB_ABUS <= OPB_RAM1_DPM_HIGHADDR)) THEN PORTB_EN <= '1' AFTER SIM_DELAY; ELSE PORTB_EN <= '0' AFTER SIM_DELAY; END IF; END PROCESS en; WE : PROCESS(OPB_BE, OPB_RNW) BEGIN IF ((OPB_BE > "0000") AND (OPB_RNW = '0'))THEN WEB <= '1' AFTER SIM_DELAY; ELSE WEB <= '0' AFTER SIM_DELAY; END IF; END PROCESS WE; ADDRB(0) <= OPB_ABUS(29) AFTER SIM_DELAY; ADDRB(1) <= OPB_ABUS(28) AFTER SIM_DELAY; ADDRB(2) <= OPB_ABUS(27) AFTER SIM_DELAY; ADDRB(3) <= OPB_ABUS(26) AFTER SIM_DELAY; ADDRB(4) <= OPB_ABUS(25) AFTER SIM_DELAY; ADDRB(5) <= OPB_ABUS(24) AFTER SIM_DELAY; ADDRB(6) <= OPB_ABUS(23) AFTER SIM_DELAY; ADDRB(7) <= OPB_ABUS(22) AFTER SIM_DELAY; ADDRB(8) <= OPB_ABUS(21) AFTER SIM_DELAY; LERAM : RAMB16_S9_S36 generic MAP( WRITE_MODE_A => "WRITE_FIRST", WRITE_MODE_B => "WRITE_FIRST", INIT_A => b"000000000", SRVAL_A => b"000000000", INIT_B => X"000000000", SRVAL_B => X"000000000", INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000", INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000") port MAP( DIA => LE_DATAOUT , DIB => LITTLE_ENDIAN_OPB_DATA , DIPA => PULLUP , DIPB => PULLUP_4 , ENA => PORTA_EN , --LEBLAZE ENB => PORTB_EN , --PORTB ENABLE FOR ADDRESS WEA => LE_WRITE_STROBE , --LEBLAZE NEVER WRITE WEB => WEB , SSRA => PULLDOWN , SSRB => PULLDOWN , CLKA => CLK , --CLOCK CLKB => CLK_INVERTED , --INVERTED CLOCK ADDRA => ADDRESS , --INSTRUCTION ADDRESS ADDRB => ADDRB , --ADDRESS FROM OPB DOA => PASS_RAM_LE_DATAIN , --INSTRUCTION FOR LEBLAZE DOB => OPB_RAM1_DATAOUT , --READ BACK DATA TO PCI ETC DOPA => OPEN , --PARITY BITS OF INSTRUCTION DOPB => OPEN ); --DON'T TRANSFER PARITY PROCESS(PORT_ID) BEGIN IF PORT_ID(7 DOWNTO 6) = "11" THEN PORTA_EN <= '1' AFTER SIM_DELAY; ELSE PORTA_EN <= '0' AFTER SIM_DELAY; END IF; END PROCESS; INT : PROCESS(RST,CLK) BEGIN IF (RST = '1') THEN INT_OPB_RAM1_INTERRUPT <= '0' AFTER SIM_DELAY; ELSIF (CLK'event AND CLK='1') THEN IF ((PORTA_EN = '1') AND (LE_READ_STROBE = '1')) THEN INT_OPB_RAM1_INTERRUPT <= '0' AFTER SIM_DELAY; ELSIF ((PORTB_EN = '1') AND (WEB = '1')) THEN INT_OPB_RAM1_INTERRUPT <= '1' AFTER SIM_DELAY; ELSE INT_OPB_RAM1_INTERRUPT <= INT_OPB_RAM1_INTERRUPT AFTER SIM_DELAY; END IF; END IF; END PROCESS; DEL1 : PROCESS(CLK) BEGIN IF (CLK'event AND CLK='1') THEN PORTB_EN_DEL1 <= PORTB_EN; END IF; END PROCESS DEL1; DATAOUT : PROCESS(OPB_RAM1_DATAOUT,PORTB_EN,OPB_RNW) BEGIN IF ((PORTB_EN = '1') AND (OPB_RNW = '1')) THEN OPB_RAM1_OPB_DBUS_OUT(31) <= OPB_RAM1_DATAOUT(0) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(30) <= OPB_RAM1_DATAOUT(1) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(29) <= OPB_RAM1_DATAOUT(2) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(28) <= OPB_RAM1_DATAOUT(3) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(27) <= OPB_RAM1_DATAOUT(4) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(26) <= OPB_RAM1_DATAOUT(5) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(25) <= OPB_RAM1_DATAOUT(6) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(24) <= OPB_RAM1_DATAOUT(7) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(23) <= OPB_RAM1_DATAOUT(8) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(22) <= OPB_RAM1_DATAOUT(9) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(21) <= OPB_RAM1_DATAOUT(10) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(20) <= OPB_RAM1_DATAOUT(11) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(19) <= OPB_RAM1_DATAOUT(12) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(18) <= OPB_RAM1_DATAOUT(13) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(17) <= OPB_RAM1_DATAOUT(14) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(16) <= OPB_RAM1_DATAOUT(15) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(15) <= OPB_RAM1_DATAOUT(16) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(14) <= OPB_RAM1_DATAOUT(17) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(13) <= OPB_RAM1_DATAOUT(18) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(12) <= OPB_RAM1_DATAOUT(19) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(11) <= OPB_RAM1_DATAOUT(20) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(10) <= OPB_RAM1_DATAOUT(21) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(9) <= OPB_RAM1_DATAOUT(22) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(8) <= OPB_RAM1_DATAOUT(23) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(7) <= OPB_RAM1_DATAOUT(24) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(6) <= OPB_RAM1_DATAOUT(25) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(5) <= OPB_RAM1_DATAOUT(26) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(4) <= OPB_RAM1_DATAOUT(27) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(3) <= OPB_RAM1_DATAOUT(28) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(2) <= OPB_RAM1_DATAOUT(29) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(1) <= OPB_RAM1_DATAOUT(30) AFTER SIM_DELAY; OPB_RAM1_OPB_DBUS_OUT(0) <= OPB_RAM1_DATAOUT(31) AFTER SIM_DELAY; ELSE OPB_RAM1_OPB_DBUS_OUT <= (OTHERS => '0'); END IF; END PROCESS DATAOUT; END A0;