text~This list has been generated out years of experience fixing other people's problems. It does not cover everything but if you think something should be added please email us at our tip
suggestions email address.(1) If multiple devices are fitted can the DONE lines be separated for debug of programming?
(2) Can INIT lines be separated to allow debug of config issues?
(3) Has Vccaux a good decoupling strategy? This can affect DCM stability.
(4) Is the general decoupling strategy a pyramid style of values/types? See XAPP623?
(5) Have the I/O configuration been checked such that no incompatible standards exist on a bank? Take care with DIN, DOUT. Run a shell test design through ISE tools to check I/O config.
(6) What is the expected power dissipation within the device? Does a heatsink need to be fitted? Run design, or model test design, through Xpower tools.
(7) Has the number of simultaneously switching outputs been checked against Xilinx recommendations?
(8) Does serial prom data line have series termination fitted? Is the placement acceptable?
(9) Is there a global reset pin or other reset mechanism?
(10) Are differential signals, especially clocks, correctly aligned to pin pairs?
(11) Do input clocks use clock friendly input pins (short internal delay)?
(12) Are there any power sequencing issues with part used? Does the PSU meet these requirements.
(13) Has programming surge current been accounted for in PSU design?
(14) Are input differential signals correctly terminated?
(15) If Virtex2-PRO / Spartan-3 does any input have 3V3 input or greater? Or Virtex2, Spartan2E greater than 3V3? Or Virtex / Spartan2 exceed 5V (some special cases 5V not allowed). Take proper precautions for voltages over these.
(16) Is the prom size large enough to load device?
(17) Do power-up programming delays cause any design issues?
(18) Do any of the outputs need guaranteed states? If so do we need extra protection externally?
(19) Does the DLL/DCM jitter cause any design issues?
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