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PCI Shipping Build1 |
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This build is based on the beta release of our own native PCI/OPB core. Cautionary note - do back up any systems before using the shipping build or Raggedstone1 in any system. Better safe that sorry. The basic configuration data of this build is as follows: BAR0 - Memory location - size 256 bytes. Is mapped to read/write our Test Target Module (details below). BAR1 - I/O location size - 128 bytes. Is mapped to read/write PCI configuration via this BAR. BAR2 - Disabled BAR3 - Disabled BAR4 - Disabled BAR5 - Disabled Vendor ID - 1AB0 Device - 0001 Class - FF00 This design contains out Test Target Module which can be read or written using BAR1 locations. The locations of this module can read but writes will not affect the returned values. The read values are as follows:
If an oscillator is fitted in the Raggedstone1 3.3V
oscillator socket then a count pattern will be seen on the 4 LEDs. MCS Files The following zipped MCS files are used to program the on-board Platforn Flash devices on Raggedstone1. Select your Raggedstone1 version for the correct file set. These designs are copyright of Enterpoint Ltd. and not for use other than with Enterpoint products without our permission. Useful PCI Utilities Craig Hart's PCI utility PCI32 is very useful. For this and other PCI information go here.
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| All trademarks
acknowledged. Xilinx, Spartan-3, Virtex-4 are trademarks of Xilinx Inc. |
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| © Copyright 2005-2007 Enterpoint Ltd. - All rights reserved. |