Darnaw1

Price

We can offer Euro and US Dollar pricing based on these prices. Please see our latest currency rates.

For OEM and quantity customers we can offer Bill of Materials customisation to fit your specific needs. This can offer cost reduction or feature enhancement depending on your requirements.

Academic pricing is available to colleges, universities and students under UAP.

FPGA - Xilinx^TM Spartan^TM-3E XC3S1200E-4FGG400C, or  XC3S1200E-4FGG400i, or XC3S1600E-4FGG400C, XC3S1600E-4FGG400I. Please note -5 commercial is same as -4 industrial grades. Order industrial grade if you need the faster grade. Automotiove grade may also be available to special order.

PGA_I/O - 219 FPGA user I/O available. 3 of the 4 bank voltages are set by user wiring. (2.5V and 1.2V available as outputs from on-board regulators, 3,3V is the input supply). 10 pins for FPGA and SPI programming supporting in target programming. Power supplies and bank voltages - 33 pins. No-connects - 11 pins.

It also is possible to operate the Darnaw1 in a reduced pinout with only the outer and inner pins of the PGA used. This configuration gives enough power pins to operate and 110 I/O and can make connections to the PGA much simpler on your target. (Note that some pins in the mid rows are used for in target programming features. This does not affect JTAG/SPI header operation on the Darnaw1 itself.) 

Flash Memory (configuration + storage) - 16Mbit SPI Flash. Usually a ST Microelectronics M25P16 but may vary from batch to batch. Enhanced versions of the Darnaw1 with 128Mbit part fitted may be available.

SDRAM - 128Mbit in 8Mx32 configuration. Usually a Micron MT48LC4M32B2 or ISSI equivalent is fitted and may vary from batch to batch. Enhanced versions of Darnaw1 with 256Mbit may be available.

Oscillator - Usually 32MHz 7x5 oscillator will be fitted. Occasionally we make vary this based on part availability. If you need a specific value please confirm with sales.

Input Power Supply - Notional single 3.3V input only needed. On board regulators for 2.5V and 1.2V.

Bank Voltages - Banks 0,1,2 are set by host by connecting suitable power to appropriate PGA pins. 2.5V is available as an output on PGA pins and can be used for variable bank voltages. Bank3 is fixed at 3.3V.

LEDs - 8 LEDs available.

SPI/JTAG - Separate SPI and JTAG 2x7 2mm Xilinx standard programming headers are implemented. There is also a jumper to hold FPGA in pre-configuration state.

Wire Wrap

Rapid Electronics stock wire wrap socket strip part number 22-1711 that we believe will mate with the PGA pins of Darnaw1. Other solutions may be available from other manufacturers like Precidip and Mill-Max.