"HOW DO I PROGRAM BROADDOWN2" - BROADDOWN2 is programmed used a JTAG cable such as our PROG1 cable or Xilinx Parallel Cable IV cable (needs flying lead set). There is a 2x6 pin header (2.54 mm) on BROADDOWN2 for a JTAG cable/programmer. These programming cables usually plug into a PC parallel port, (Xilinx USB cable also available), and using Xilinx Impact software the Spartan-3 FPGA, or the Platform Flash, can be programmed from appropriate data output from the ISE toolset.

"WHY ARE THERE 2 JTAG CHAINS" - Most users don't want to change the CPLD contents so to avoid accidental programming we simply made the chain separate. There is capability to join the chains on BROADDOWN2 but it has never been tried and we can't support this feature at present.

"CAN I PROGRAM THE FPGA CONFIGURATION FLASH MEMORIES FROM PCI" - We have hardware support for this feature built into BROADDOWN2 via the on-board CPLDs and the Expansion Bus. However this feature has not been tested sufficiently to offer more than general advice for a real implementation. We do intent to develop this feature in BROADDOWN2/3/4 further and a software GUI may become available to assist in this in the future.

"WHAT IS THE EXPANSION BUS" - The Expansion Bus is a 9 bit connection between the Spartan-3 FPGA and 3 Coolrunner-II CPLDs that control power and advanced programming features. As yet we have not defined a usage for this bus and customers may set their own standard. However we do intend to set a standard usage for the bus that we can offer support on and increase the "shipped" functionality of BROADDOWN2. 

"WHERE DO I GET A SOFTWARE DRIVER" - BROADDOWN2 has been pinned out to use a Xilinx PCI Core (additional purchase). Jungo produces drivers for XP, WIN2K, Linux for the Xilinx PCI Core. You are also free to use other PCI Cores although we have not used any other products and subsequently can't offer support on them.

"CAN I USE DMA WITH THIS BOARD" - If the PCI Core that you use does then yes. Full functionality for INITIATOR functions is supported by the Xilinx PCI Core.

"WHAT VERSION OF PCI IS SUPPORTED BY BROADDOWN2" - That depends on the PCI Core that you select for your FPGA design. The Xilinx PCI Core is at version 3.0 of the PCI specification. Technically the bus switches used to protect the Spartan-3 for 5V PCI make the electrical interface non-compliant but we have never seen any problems under our testing, or had any reports from customers, in BROADDOWN2 or MINI-CAN. MINI-CAN was derived from BROADDOWN2 and they have virtually identical PCI interfaces.

"CAN I USE BROADDOWN2 STAND-ALONE" - Use the Disk Drive Connector to supply 5V. 12V is optional. Otherwise you can use our PCI I/O Expansion Module. The latter allows the PCI interface to be reused as a 5V tolerant I/O and allows power (5V dc) to be connected without soldering to the BROADDOWN2.

 "WHAT SPARTAN-3 IS FITTED TO BROADDOWN2" - XC3S400-4FG456C (BD2-400) or XC3S1000-4FG456C (BD2-1000) or XC3S1500-4FG456C (BD2-1500)  are fitted to BROADDOWN2. Faster speed grades, or industrial temperature grades, can be fitted at extra cost.

"WHY DO YOU FIT THE LARGE PACKAGE WHEN YOU ARE NOT USING ALL THE I/O" - In the XC3S400 variant all I/Os are used. To keep a common PCB the extra I/O of the XC3S1000/1500 are not currently supported. By using the larger package a higher number of output I/O can switch at the same time. It also helps of component stock management to share parts with our other products. See Xilinx SSO guidelines for more information on this.

"WHY DOES THE DDR2 INTERFACE PINOUT CAUSE FAILURES AT MAPPING" - Currently we are not supporting the DDR2 socket for memory operations. However the main problem is usually the number of clocks that your design has. Spartan-3, and its parent Virtex-II, have clock structures shared across pairs of I/O cells. Two clocks (input register) and two clocks (output register) can be used on these pairs of I/O cells. Many DDR cores use 2 clocks for DQ lines and a different clock for DQS signals. This gives a count of three that simply does not fit. We encountered this issue in the early days of Virtex-II release and designed our own DDR core to be "light" on clocks. We designed Broaddown2 to represent a lowish cost, real-life type, board layout. Consequently the pinout was chosen for layout and only tested against our own DDR Intellectual Property. Given that most other DDR Cores are not designed the way our is we will attempt to remove this restriction in later Broaddown2's. Broaddown3 and Broaddown4 will not have this restriction.

"IS THERE A ON/OFF CHIP FEEDBACK PIN PAIR I CAN USE TO ADJUST TIMING ON MY DDR2 IMPLEMENTATION" - Currently we are not supporting the DDR2 socket for memory operations. However there is a good pair of usually un-commited signals that run from Bank4 of the FPGA to adjacent pins on the right hand side YHS and GFS connectors. They are actually the Spartan-3 (FG456 package) differental, or single, clock(or I/O) pins AA12 and AB12 from the Spartan-3. They connect to pins C20 and C21 of the YFS and GFZ connectors and can be easily connected particularly on the GFZ connector. Trace run on these is about 31 MM each. SODIMM traces are typically in the length range 55 to 65 MM. Because AA12 and AB12 are clock inputs they have "fast" connections to relevant BUFGs and DCMs. Pin A1 is the top right pin of YFS as you face the front (PCI is at the bottom) of Broaddown2. Pins run 1 to 40 vertically down.  GFZ connector is a mirror of YFS.

"WHY CAN'T WE HAVE A FULL 64 BIT DATA DDR2 INTERFACE " - Currently we are not supporting the DDR2 socket for memory operations. The size of interface was a compromise between potential users. The DDR2 interface uses almost fully 3 banks of the FPGA. To use more would have limited the size of the DIL headers and the easy expansion capabilities. We believe that we hit a good compromise between these. Even with a XC3S1500 fitted there are not enough I/O for a full implementation in 3 banks.

"I DON'T WANT DDR2 INTERFACE CAN I USE THE I/O" - Yes we have an optional SODIMM like module that allows access to most of the signals on a 2 mm header. Currently we are not supporting the DDR2 socket for memory operations.

"CAN I USE DDR1 SODIMMS" - No, unlike full size DIMMs DDR1 and DDR2 SODIMMS are incompatible in their pinout. Currently we are not supporting the DDR2 socket for memory operations.

"HOW STABLE ARE THE NEGATIVE VOLTAGE SUPPLIES" - Not very as we run the LT1054 in a simple inverting mode. There is a load regulation voltage drop as current increases. If you need stable negative voltages you need to post-regulate the LT1054 output/s or use an additional circuit. These supplies were only intended to allow simple things like dual rail op-amps to operate.

"MY PIN ON THE LHS DIL HEADER IS STUCK AT GND (0V)" - Please check that the "EDGE CONNECTOR" has not become un-seated and is touching the metal bracket.