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PCI Core FAQ
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"I HAVE MODULES MAPPED INTO I/O SPACE AND RETURNING CORRECT DATA ON THE INTERNAL OPB BUS BUT NOT OUT THE PCI CORE ONTO PCI" - Ensure that modules that cannot return data in a burst (contiguous data every clock) are mapped into non-burstable OPB address space. The burstable address area is set using BURSTABLE_ADDRESS_LOWER and BURSTABLE_ADDRESS_UPPER inputs to the core. Marking areas as non-burstable to the PCI does not preclude local masters bursting to modules over the OPB bus.
"WHICH VERSION OF ISE DO I NEED TO USE THE PCI CORE" - We believe that all versions of ISE work with the core and have no known issues with any version of ISE.
"HOW MANY BARS DOES THE CORE SUPPORT" - The lite version of the core supports 2 BARs - one I/O, one Memory. The full version supports up 1-6 BARs. These can be individually set as I/O or Memory space.
"DOES THE OPB OPERATING FREQUENCY NEED TO MATCH THAT OF THE PCI" - Yes normally you do need to match the OPB interface in frequency. We have placed this restriction because it allows us minimise the size and maximise the performance of the core. It is possible that external logic can be placed between the core and the main OPB bus to allow the OPB to operate at different frequencies but with the proviso that you must expect a drop in performance in the PCI interface. We will not support such adaptations unless under a paid for service contract.
"CAN THE CORE OPERATE AT HIGHER FREQUENCIES THAN 33MHZ" - We expect that slightly higher frequencies can be used in Spartan-3 FPGAs but this is not tested or supported. It is likely that Virtex-4 and Virtex-5 based use may be capable of running at 66MHz but as yet this has not been tested and is not supported at present. We are unlikely to do any more work to achieve 66MHz in Spartan-3 devices unless a customer specifically commissions us to do it. Our PCI-E core is under development and is expected that is core will be used in high bandwidth applications rather than conventional PCI.
"DOES EAR APPLY" - The design and support for this core is carried out in the United Kingdom and is not subject to US regulation. UK export regulations may apply however and any military application is likely to need an export license.
"WHAT DRIVER SUPPORT IS THERE" - We expect to have drivers for Windows and Linux available shortly.
"CAN YOU SUPPORT 64 BIT" - At present we don't but we expect that we can can with a relatively small amount of work. Anyone needing to purchase a 64 bit implementation should talk to the IP sales team.
"DO YOU HAVE REFERENCE DESIGNS" - Our shipping build design for Raggedstone1 will be made available soon as a reference design. We expect to make other designs available in the coming months.
"CAN WE MIGRATE LICENSES TO ASIC TECHNOLOGY" - ASIC migration licenses will be available for those that want to start a design in a FPGA architecture and want to migrate to ASIC. At present we have not proven the design in ASIC technologies and customers should make their own pre-silicon verification of the core before use in a ASIC.