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Drigmorn1 Pinout Constraints File
Drigmorn1
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Waggle Test
This design is very simple and consists of a counter
which uses the onboard 40Mhz oscillator as a clock source. Different
bits of the counter are output to the I/O pins and the 3 LEDs. When the
SpartanTM-3E
FPGA is configured the LEDs will flash at different rates indicating
that the design is running.
VHDL source file is
here.
UCF file is here.
Turning Your Drigmorn1 into a 8086 processor.
HT-LAB have implemented their CPU86 on Drigmorn1. To obtain
lab materials and applications information go
http://www.ht-lab.com/hardware/drigmorn1/drigmorn1.html.